Taiwan Semiconductor Manufacturing Company (TSMC) and the Japanese government recently agreed to launch a ¥37 billion ($337.4 million) electronic component research project. The initiative aims to develop groundbreaking microelectronic technologies, and 3D integrated circuit packaging is a focus area.

The contract chipmaker and the Kantei are co-funding an R&D center in Tsukuba, Japan, which will open sometime in 2022.

In addition to TSMC, around 20 Japanese semiconductor companies will participate in the potentially game-changing program.

Why TSMC is Researching 3DIC Packaging Technology

In April, TMSC announced it would spend $100 billion to upgrade its production capabilities over the next three years. The corporation intends to use that capital to build new facilities to meet intense global demand for its services. It also wants to assert its status as the world’s most technologically sophisticated pure-play foundry by expanding its range of industry-leading manufacturing techniques.

For TSMC, developing 3DIC packaging technology is an area rife with possibility.

Traditionally, firms have marked advances in semiconductor technology by setting new Moore’s Law benchmarks; the biannual doubling of transistor density. Last year, the Taiwanese chipmaker became the first company to use a 5nm manufacturing process in mass production. The node reportedly enabled Apple to create iPhone processors with 11.8 billion transistors and a 40 percent generational performance improvement.

Although TSMC hopes to launch its 3nm process next year, it is now grappling with chip lithography limitations.

Eventually, the laws of physics will prevent the foundry from etching significantly more transistors onto its components every two years. However, 3DIC packaging, which involved stacking silicon wafers and connecting them vertically, allows for iterative upgrades outside Moore’s Law.

Furthermore, TSMC’s Tsukuba-based R&D center will benefit from the contributions of several Japanese semiconductor manufacturing technology companies. Asahi Kasei, a material producer renowned for its ultrathin wiring, is part of Tokyo’s public-private development initiative. Mitsui Chemicals, which offers technology to assemble high-density silicon wafers, is also participating in the initiative.

Given the firms involved, TSMC’s Japanese venture has the potential to introduce revolutionary microelectronics solutions.

Why Japan Forged a Partnership with TSMC

A little over 30 years ago, Japan had a dominant position in the global semiconductor industry. Six of the nation’s homegrown companies appeared on the list of top 10 chipmakers by market share. However, its domestic enterprises only accounted for 10 percent of the field in 2019. As time passed, Americans, South Korean, and Taiwanese design houses and manufacturing corporations out-innovated the region's providers.

Tokyo intends to spark a revival of its microelectronics field with initiatives like its partnership with TSMC.

From an economic perspective, the Japanese government’s actions make a lot of sense. Gartner determined the global IC sector reached $449.8 billion in value last year, up 7.3 percent year-over-year. The country could meaningfully better its gross domestic product by becoming a bigger player in the worldwide chip marketplace.

Since the Kantei is keen to restore Japan's status as a semiconductor development hub, partnering with TSMC is a smart move. Recently, the foundry has shattered its previous revenue records because Big Tech firms the world over have sought out its best-in-class technology. That means it is the best possible facilitator of the government’s long-term microelectronics industry ambitions.